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cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 18-mbit ddr ii sram four-word burst architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-58906 rev. *d revised july 20, 2011 18-mbit ddr ii sram four-word burst architecture features 18-mbit density (2 m 8, 2 m 9, 1 m 18, 512 k 36) 333-mhz clock for high bandwidth four-word burst for reducing address bus frequency double data rate (ddr) interfaces (data transferred at 666 mhz) at 333 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for ou tput data (c and c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems synchronous internally self-timed writes ddr ii operates with 1.5 cycle read latency when doff is asserted high operates similar to ddr i device with one cycle read latency when doff is asserted low 1.8 v core power supply with hstl inputs and outputs variable drive hstl output buffers expanded hstl output voltage (1.4 v?v dd ) ? supports both 1.5 v and 1.8 v i/o supply available in 165-ball fbga package (13 15 1.4 mm) offered in both pb-free and non pb-free packages jtag 1149.1 compatible test access port phase locked loop (pll) for accurate data placement configurations cy7c1317kv18 ? 2 m 8 cy7c1917kv18 ? 2 m 9 cy7c1319kv18 ? 1 m 18 cy7c1321kv18 ? 512 k 36 functional description the cy7c1317kv18, cy7c1917kv18, cy7c1319kv18, and cy7c1321kv18 are 1.8 v synchronous pipelined srams equipped with ddr ii architecture. the ddr ii consists of an sram core with advanced synchronous peripheral circuitry and a two-bit burst counter. addresses for read and write are latched on alternate rising edges of the input (k) clock. write data is registered on the rising edges of both k and k . read data is driven on the rising edges of c and c if provided, or on the rising edge of k and k if c/c are not provided. each address location is associated with four 8-bit words in the case of cy7c1317kv18 and four 9-bit words in the case of cy7c1917kv18 that burst sequentially into or out of the device. the burst counter always starts with a ?00? internally in the case of cy7c1317kv18 and cy7c1917kv18. for cy7c1319kv18 and cy7c1321kv18, the burst counter takes in the least two significant bits of the external address and bursts four 18-bit words in the case of cy7c1319kv18, and four 36-bit words in the case of cy7c1321kv18, sequentially into or out of the device. asynchronous inputs include an output impedance matching input (zq). synchronous data outputs (q, sharing the same physical pins as the data inputs, d) are tightly matched to the two output echo clocks cq/cq , eliminating the need to capture data separately from each individual ddr sram in the system design. output data clocks (c/c ) enable maximum system clocking and data synchronization flexibility. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c (or k or k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide description 333 mhz 300 mhz 250 mhz 200 mhz 167 mhz unit maximum operating frequency 300 300 250 200 167 mhz maximum operating current 8 370 350 320 280 260 ma 9 370 350 320 280 260 18 370 350 320 290 270 36 440 420 370 330 300 [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 2 of 33 logic block diagram (cy7c1317kv18) logic block diagram (cy7c1917kv18) write reg clk a (18:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 16 32 8 nws [1:0] v ref write add. decode 16 19 c c 8 ld control r/w doff 512 k x 8 array 512 k x 8 array 8 write reg write reg write reg 512 k x 8 array 512 k x 8 array 8 8 dq [7:0] 8 cq cq write reg clk a (18:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 18 36 9 bws [0] v ref write add. decode 18 19 c c 9 ld control r/w doff 512 k x 9 array 512 k x 9 array 9 write reg write reg write reg 512 k x 9 array 512 k x 9 array 9 9 dq [8:0] 9 cq cq [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 3 of 33 logic block diagram (cy7c1319kv18) logic block diagram (cy7c1321kv18) write reg clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 36 72 18 bws [1:0] v ref write add. decode 36 20 c c 18 ld control r/w doff 256 k x 18 array 256 k x 18 array 18 write reg write reg write reg 256 k x 18 array 256 k x 18 array 18 18 burst logic 2 a (1:0) 18 a (19:2) dq [17:0] 18 cq cq write reg clk a (18:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 72 144 36 bws [3:0] v ref write add. decode 72 19 c c 36 ld control r/w doff 128 k x 36 array 128 k x 36 array 36 write reg write reg write reg 128 k x 36 array 128 k x 36 array 36 36 burst logic 2 a (1:0) 17 a (18:2) dq [35:0] 36 cq cq [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 4 of 33 contents pin configuration ............................................................. 5 165-ball fbga (13 15 1.4 mm) pinout .................. 5 pin definitions .................................................................. 7 functional overview ........................................................ 9 read operations ......................................................... 9 write operations ......................................................... 9 byte write operations ................................................. 9 single clock mode .............. ........................................ 9 ddr operation ............................................................ 9 depth expansion ....................................................... 10 programmable impedance ........ ......................... ....... 10 echo clocks .......... .......................................... .......... 10 pll ............................................................................ 10 application example ...................................................... 11 truth table ...................................................................... 11 burst address table ................ ............................ .......... 12 write cycle descriptions ............................................... 12 write cycle descriptions ............................................... 13 write cycle descriptions ............................................... 13 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 14 disabling the jtag feature ...................................... 14 test access port?test clock ................................... 14 test mode select (tms) ........................................... 14 test data-in (tdi) ..................................................... 14 test data-out (tdo) ................................................. 14 performing a tap re set ........................................... 14 tap registers ........................................................... 14 tap instruction set ................................................... 14 tap controller state diagram ....................................... 16 tap controller block diagram ...................................... 17 tap electrical characteristics ...................................... 17 tap ac switching characteristics ............................... 18 tap timing and test conditions .................................. 18 identification register definitions ................................ 19 scan register sizes ....................................................... 19 instruction codes ........................................................... 19 boundary scan order .................................................... 20 power up sequence in ddr ii sram ........................... 21 power up sequence ................................................. 21 pll constraints ......................................................... 21 maximum ratings ........................................................... 22 operating range ............................................................. 22 neutron soft error immunity ......................................... 22 electrical characteristics ............................................... 22 dc electrical characteristics ..................................... 22 ac electrical characteristics ..................................... 24 capacitance .................................................................... 25 thermal resistance ........................................................ 25 ac test loads and waveforms ..................................... 25 switching characteristics .............................................. 26 switching waveforms .................................................... 28 ordering information ...................................................... 29 ordering code definitions ..... .................................... 29 package diagram ............................................................ 30 acronyms ........................................................................ 31 document conventions ................................................. 31 units of measure ....................................................... 31 document history page ................................................. 32 sales, solutions, and legal information ...................... 33 worldwide sales and design s upport ......... .............. 33 products .................................................................... 33 psoc solutions ......................................................... 33 [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 5 of 33 pin configuration the pin configurations for cy7c1317kv18, cy7c1917kv18, cy7c1319kv18, and cy7c1321kv18 follow. [1] 165-ball fbga (13 15 1.4 mm) pinout cy7c1317kv18 (2 m 8) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/72m a r/w nws 1 k nc/144m ld anc/36mcq b nc nc nc a nc/288m k nws 0 ancncdq3 c nc nc nc v ss ancav ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq4 v ddq v ss v ss v ss v ddq nc nc dq2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc nc dq5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq1 nc k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc dq6 nc v ddq v ss v ss v ss v ddq nc nc dq0 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss aaav ss nc nc nc p nc nc dq7 a a c a a nc nc nc r tdotckaaac aaatmstdi cy7c1917kv18 (2 m 9) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/72m a r/w nc k nc/144m ld anc/36mcq b nc nc nc a nc/288m k bws 0 ancncdq3 c nc nc nc v ss ancav ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq4 v ddq v ss v ss v ss v ddq nc nc dq2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc nc dq5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq1 nc k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc dq6 nc v ddq v ss v ss v ss v ddq nc nc dq0 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss aaav ss nc nc nc p nc nc dq7 a a c a a nc nc dq8 r tdotckaaac aaatmstdi note 1. nc/36m, nc/72m, nc/144m, and nc/288m are not connected to the die and can be tied to any voltage level. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 6 of 33 cy7c1319kv18 (1 m 18) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/72m a r/w bws 1 k nc/144m ld anc/36mcq b nc dq9 nc a nc/288m k bws 0 ancncdq8 c nc nc nc v ss aa0a1v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss aaav ss nc nc nc p nc nc dq17 a a c a a nc nc dq0 r tdotckaaac aaatmstdi cy7c1321kv18 (512 k 36) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/144m nc/36m r/w bws 2 k bws 1 ld anc/72mcq b nc dq27 dq18 a bws 3 kbws 0 ancncdq8 c nc nc dq28 v ss aa0a1v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss aaav ss nc nc dq10 p nc nc dq26 a a c a a nc dq9 dq0 r tdotckaaac aaatmstdi pin configuration (continued) the pin configurations for cy7c1317kv18, cy7c1917kv18, cy7c1319kv18, and cy7c1321kv18 follow. [1] 165-ball fbga (13 15 1.4 mm) pinout [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 7 of 33 pin definitions pin name i/o pin description dq [x:0] input output- synchronous data input output signals. inputs are sampled on the rising edge of k and k clocks during valid write operations. these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k when in single clock mode. when read access is deselected, q [x:0] are automatically tristated. cy7c1317kv18 ? dq [7:0] cy7c1917kv18 ? dq [8:0] cy7c1319kv18 ? dq [17:0] cy7c1321kv18 ? dq [35:0] ld input- synchronous synchronous load. this input is brought low when a bus cycle sequence is defined. this definition includes address and read/write direction. all transacti ons operate on a burst of 4 data (two clock periods of bus activity). nws 0 , nws 1 input- synchronous nibble write select 0, 1 ?? active low (cy7c1317kv18 only). sampled on the rising edge of the k and k clocks during write operations. used to select which nibble is writte n into the device during the current portion of the write operations. nib bles not written remain unaltered. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all the nibble write selects are sampled on the same edge as the data. deselecting a nibble write select ignores the corresponding nibble of data and it is not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ?? active low. sampled on the rising edge of the k and k clocks during write operations. used to select which byte is wri tten into the device during the current portion of the write operations. bytes not written remain unaltered. cy7c1917kv18 ? bws 0 controls d [8:0] cy7c1319kv18 ?? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1321kv18 ?? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] . all the byte write selects are sampled on the same edge as the data. deselecting a byte write select ignores the corresponding byte of data and it is not written into the device. a, a0, a1 input- synchronous address inputs. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2 m 8 (4 arrays each of 512 k 8) for cy7c1317kv18 and 2 m 9 (4 arrays each of 512 k 9) for cy7c1917kv18, 1 m 18 (4 arrays each of 256 k 18) for cy7c1319kv18, and 512 k 36 (4 arrays each of 128 k 36) for cy7c1321kv18. cy7c1317kv18 ? because the least two significant bits of the address internally are ?00?, only 19 external address inputs are needed to access the entire memory array. cy7c1917kv18 ? because the least two significant bits of the address internally are ?00?, only 19 external address inputs are needed to access the entire memory array. cy7c1319kv18 ? a0 and a1 are the inputs to the burs t counter. these are incremented internally in a linear fashion. 20 address inputs are needed to access the entire memory array. cy7c1321kv18 ? a0 and a1 are the inputs to the burs t counter. these are incremented internally in a linear fashion. 19 address inputs are needed to access the entire memory array. r/w input- synchronous synchronous read/write input. when ld is low, this input designates the access type (read when r/w is high, write when r/w is low) for the loaded address. r/w must meet the setup and hold times around the edge of k. c input clock positive input clock for output data. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example on page 11 for more information. c input clock negative input clock for output data. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example on page 11 for more information. k input clock positive input clock input. the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 8 of 33 k input clock negative input clock input. k is used to capture synchronous data being presented to the device and to drive out data through q [x:0] when in single clock mode. cq output clock cq referenced with respect to c. this is a free running clock and is synchronized to the input clock for output data (c) of the ddr ii. in single clock mode, cq is generated with respect to k. the timing for the echo clocks is shown in switching characteristics on page 26 . cq output clock cq referenced with respect to c . this is a free running clock and is synchronized to the input clock for output data (c ) of the ddr ii. in single clock mode, cq is generated with respect to k . the timing for the echo clocks is shown in switching characteristics on page 26 . zq input output impedance matching input. this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 rq, where rq is a resistor connected between zq and ground. alternatively, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be conn ected directly to gnd or left unconnected. doff input pll turn off ?? active low. connecting this pin to ground turns off the pll inside the device. the timing in the pll turned off operation is different from that listed in this data sheet. for normal operation, this pin is connected to a pull up through a 10 k ohm or less pull up resistor. the device behaves in ddr i mode when the pll is turned off. in this mode, the device can be operated at a frequency of up to 167 mhz with ddr i timing. tdo output tdo for jtag. tck input tck pin for jtag. tdi input tdi pin for jtag. tms input tms pin for jtag. nc n/a not connected to the die. can be tied to any voltage level. nc/36m n/a not connected to the die. can be tied to any voltage level. nc/72m n/a not connected to the die. can be tied to any voltage level. nc/144m n/a not connected to the die. can be tied to any voltage level. nc/288m n/a not connected to the die. can be tied to any voltage level. v ref input- reference reference voltage input. static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device. v ss ground ground for the device. v ddq power supply power supply inputs for the outputs of the device. pin definitions (continued) pin name i/o pin description [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 9 of 33 functional overview the cy7c1317kv18, cy7c1917kv18, cy7c1319kv18, and cy7c1321kv18 are synchronous pipelined burst srams equipped with a ddr interface, which operates with a read latency of one and half cycles when doff pin is tied high. when doff pin is set low or connected to v ss the device behaves in ddr i mode with a read latency of one clock cycle. accesses are initiated on the rising edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edg e of the output clocks (c/c , or k/k when in single clock mode). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the rising edge of the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the output clocks (c/c , or k/k when in single-clock mode). all synchronous control (r/w , ld , bws [0:x] ) inputs pass through input registers controlled by the ri sing edge of the input clock (k). cy7c1319kv18 is described in the following sections. the same basic descriptions apply to cy7c1317kv18, cy7c1917kv18, and cy7c1321kv18. read operations the cy7c1319kv18 is organized internally as four arrays of 256 k 18. accesses are completed in a burst of four sequential 18-bit data words. read operat ions are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to address inputs is stored in the read address register and the least two significant bits of the address are presented to the bur st counter. the burst counter increments the address in a linear fashion. following the next k clock rise, the corresponding 18-bit word of data from this address location is driven onto q [17:0] , using c as the output timing reference. on the subsequent rising edge of c the next 18-bit data word from the address location generated by the burst counter is driven onto q [17:0] . this process continues until all four 18-bit data words are driven out onto q [17:0] . the requested data is valid 0.45 ns from the rising edge of the output clock (c or c , or k and k when in single clock mode, for 200 mhz and 250 mhz device). to maintain the internal logic, each read access must be allowed to complete. each read access consists of four 18-bit data words and ta kes two clock cycles to complete. therefore, read accesses to the device cannot be initiated on two consecutive k clock rises. the internal logic of the device ignores the second read request. read accesses can be initiated on every other k clock rise. doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks (c/c or k/k when in single-clock mode). the cy7c1319kv18 first completes the pending read transactions, when read access is deselected. synchronous internal circuitry automatically tristates the output following the next rising edge of the positive output clock (c). this enables a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are init iated by asserting r/w low and ld low at the rising edge of the positive input clock (k). the address presented to address inputs is stored in the write address register and the least two significant bits of the address are presented to the burst count er. the burst counter increments the address in a linear fashion. on the following k clock rise the data presented to d [17:0] is latched and stored into the 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. this process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the sram. the 72 bits of data are then written into the memory array at the specified location. therefore, write accesses to the device cannot be initiated on two consecutive k clock rises. the internal logic of the device ignores the second wr ite request. writ e accesses can be initiated on every other rising edge of the positive input clock (k). doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when write access is deselected, the device ignores all inputs after the pending write operations are completed. byte write operations byte write operations are supp orted by the cy7c1319kv18. a write operation is initiated as described in the write operations section. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte wr ite select input during the data portion of a write latches the dat a being presented and writes it into the device. deasserting the byte write select input during the data portion of a write enab les the data stored in the device for that byte to remain unaltered. this feature is used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1319kv18 is used with a single clock that controls both the input and output registers. in this mode the device recognizes only a single pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, tie c and c high at power on. this function is a strap optio n and not alterable during device operation. ddr operation the cy7c1319kv18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. the cy7c1319kv18 requires a single no operation (nop) cycle when transitioning from a read to a write cycle. at higher frequencies, some applications may require a second nop cycle to avoid contention. if a read occurs after a write cycle, address and data for the write are stored in registers. the wr ite information must be stored because the sram cannot perform the last word write to the array without conflicting with th e read. the data stays in this [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 10 of 33 register until the next write cycle occurs. on the first write cycle after the read(s), the stored data fr om the earlier write is written into the sram array. this is called a posted write. if a read is performed on the same address on which a write is performed in the previous cycl e, the sram reads out the most current data. the sram does this by bypassing the memory array and reading the data from the registers. depth expansion depth expansion requir es replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5 the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq =1.5 v. the output impedance is adjusted ev ery 1024 cycles at power up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the ddr ii to simplify data capture on high speed systems. two echo clocks are generated by the ddr ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free running clocks and are synchronized to the output clock of the ddr ii. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timing for the ec ho clocks is shown in switching characteristics on page 26 . pll these chips use a pll that is designed to function between 120 mhz and the specified maximum clock frequency. during power up, when the doff is tied high, the pll is locked after 20 ? s of stable clock. the pll can also be reset by slowing or stopping the input clocks k and k for a minimum of 30 ns. however, it is not necessary to reset the pll to lock it to the desired frequency. the p ll automatically locks 20 ? s after a stable clock is presented. the pll may be disabled by applying ground to the doff pin. when the pll is turned off, the device behaves in ddr i mode (with one cycle latency and a longer access time). [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 11 of 33 application example figure 1 shows two ddr ii used in an application. figure 1. application example vterm = 0.75v vterm = 0.75v r = 50ohms r = 250ohms ld# c c#r/w# dq a k ld# c c#r/w# dq a k sram#1 sram#2 r = 250ohms bus master (cpu or asic) dq addresses cycle start# r/w# return clk source clk return clk# source clk# echo clock1/echo clock#1 echo clock2/echo clock#2 zq cq/cq# k# zq cq/cq# k# truth table the truth table for the cy7c1317kv18, cy7c1917kv 18, cy7c1319kv18, and cy7c1321kv18 follows. [2, 3, 4, 5, 6, 7] operation k ld r/w dq dq dq dq write cycle: load address; wait one cycle; input write data on four consecutive k and k rising edges. l?h l l d(a1) at k(t + 1) ? d(a2) at k (t + 1) ? d(a3) at k(t + 2) ? d(a4) at k (t + 2) ? read cycle: load address; wait one and a half cycle; read data on four consecutive c and c rising edges. l?h l h q(a1) at c (t + 1)? q(a2) at c(t + 2) ? q(a3) at c (t + 2)? q(a4) at c(t + 3) ? nop: no operation l?h h x high z high z high z high z standby: clock stopped stopped x x previous state previous state previous state previous state notes 2. x = ?don?t care?, h = logic high, l = logic low, ? ? represents rising edge. 3. device powers up deselected with the outputs in a tristate condition. 4. on cy7c1319kv18 and cy7c1321kv18, ?a1? represents address locati on latched by the devices when transaction was initiated and ?a2?, ?a3?, ?a4? represents the addresses sequence in the burst. on cy7c1317kv18 and cy7c1917kv18, ?a1? represents a + ?00? and ?a2? represents a + ?01?, ?a3? represents a + ?10? and ?a4? represents a + ?11?. 5. ?t? represents the cycle at which a read/wri te operation is started. t + 1 and t + 2 are the first and second clock cycles su cceeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but permi ts most rapid restart by overcoming transmission line charging symmetrically. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 12 of 33 burst address table (cy7c1319kv18, cy7c1321kv18) first address (external) second address (internal) third address (internal) fourth address (internal) x..x00 x..x01 x..x10 x..x11 x..x01 x..x10 x..x11 x..x00 x..x10 x..x11 x..x00 x..x01 x..x11 x..x00 x..x01 x..x10 write cycle descriptions the write cycle description table for cy 7c1317kv18 and cy7c1319kv18 follows. [8, 9] bws 0 / nws 0 bws 1 / nws 1 k k comments l l l?h ? during the data portion of a write sequence ? cy7c1317kv18 ?? both nibbles (d [7:0] ) are written into the device. cy7c1319kv18 ?? both bytes (d [17:0] ) are written into the device. l l ? l?h during the data portion of a write sequence: cy7c1317kv18 ?? both nibbles (d [7:0] ) are written into the device. cy7c1319kv18 ?? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence: cy7c1317kv18 ?? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1319kv18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence ? cy7c1317kv18 ?? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1319kv18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence ? cy7c1317kv18 ?? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1319kv18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence ? cy7c1317kv18 ?? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1319kv18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. notes 8. x = ?don?t care?, h = logic high, l = logic low, ? ? represents rising edge. 9. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requi rements are achieved. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 13 of 33 write cycle descriptions the write cycle description tabl e for cy7c1917kv18 follows. [10, 11] bws 0 k k comments l l?h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l?h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l?h ? no data is written into the device during this portion of a write operation. h ? l?h no data is written into the device during this portion of a write operation. write cycle descriptions the write cycle description ta ble for cy7c1321kv18 follows. [10, 12] bws 0 bws 1 bws 2 bws 3 k k comments l l l l l?h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l?h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a wr ite sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h h l?h ? no data is written into the device during this portion of a write operation. h h h h ? l?h no data is written into the device during this portion of a write operation. notes 10. x = ?don?t care?, h = logic high, l = logic low, ? ? represents rising edge. 11. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. 12. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 14 of 33 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. th is part is fully compliant with ieee standard #1149. 1-2001. the tap operates using jedec standard 1.8 v io logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram on page 16 . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 19 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and is performed when the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram te st circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions are serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 17 . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a reset state, as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions are used to capture the contents of the input and output ring. the boundary scan order on page 20 shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and is shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in identification register definitions on page 19 . tap instruction set eight different instructions ar e possible with the three-bit instruction register. all co mbinations are listed in instruction codes on page 19 . three of these instru ctions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifte d in, the tap controller must be moved into the update-ir state. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 15 of 33 idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is supplied during the update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instructi on. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan regi ster cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when requir ed, that is, while the data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus tristate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bi t places the output bus into a high z condition. this bit is set by entering the sample/preload or extest command, and then shifting the desir ed bit into that cell, during the shift-dr state. during updat e-dr, the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is pre-set high to enable the output when the device is powered up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 16 of 33 tap controller state diagram the state diagram for the tap controller follows. [13] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 13. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 17 of 33 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range parameter [14, 15, 16] description test conditions min max unit v oh1 output high voltage i oh = ?? 2.0 ma 1.4 ? v v oh2 output high voltage i oh = ?? 100 ? a1.6?v v ol1 output low voltage i ol = 2.0 ma ? 0.4 v v ol2 output low voltage i ol = 100 ? a?0.2v v ih input high voltage ? 0.65 v dd v dd + 0.3 v v il input low voltage ? ?0.3 0.35 v dd v i x input and output load current gnd ? v i ? v dd ?5 5 ? a notes 14. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics on page 22 . 15. overshoot: v ih (ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5 v (pulse width less than t cyc /2). 16. all voltage referenced to ground. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 18 of 33 tap ac switchi ng characteristics over the operating range parameter [17, 18] description min max unit t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high 20 ? ns t tl tck clock low 20 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns tap timing and test conditions figure 2 shows the tap timing and test conditions. [18] figure 2. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9 v 50 ? 1.8 v 0 v all input pulses 0.9 v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 17. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 18. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 19 of 33 identification regi ster definitions instruction field value description cy7c1317kv18 cy7c1917kv18 cy7c1319kv18 cy7c1321kv18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010100011000101 11010100011001101 11010100011010101 11010100011100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register wit h the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents . places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output ring co ntents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 20 of 33 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 2j 16 p2 99 g5 75 b8 53 k 2 6n 30 11f 58 5a 86 3j 3 7p 31 11g 59 4a 87 2k 47 n 3 29 f 6 05 c 8 81 k 5 7r 33 10f 61 4b 89 2l 6 8r 34 11e 62 3a 90 3l 7 8p 35 10e 63 1h 91 1m 8 9r 36 10d 64 1a 92 1l 9 11p 37 9e 65 2b 93 3n 10 10p 38 10c 66 3b 94 3m 11 10n 39 11d 67 1c 95 1n 12 9p 40 9c 68 1b 96 2m 13 10m 41 9d 69 3d 97 3p 14 11n 42 11b 70 3c 98 2n 15 9m 43 11c 71 1d 99 2p 16 9n 44 9b 72 2c 100 1p 17 11l 45 10b 73 3e 101 3r 18 11m 46 11a 74 2d 102 4r 19 9l 47 internal 75 2e 103 4p 20 10l 48 9a 76 1e 104 5p 21 11k 49 8b 77 2f 105 5n 22 10k 50 7c 78 3f 106 5r 23 9j 51 6c 79 1g 24 9k 52 8a 80 1f 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1j [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 21 of 33 power up sequence in ddr ii sram ddr ii srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence apply power and drive doff either high or low (all other inputs can be high or low). ? apply v dd before v ddq . ? apply v ddq before v ref or at the same time as v ref . ? drive doff high. provide stable doff (high), power and clock (k, k ) for 20 ? s to lock the pll. pll constraints pll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var . the pll functions at frequencies down to 120 mhz. if the input clock is unstable and the pll is enabled, then the pll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide 20 ? s of stable clock to relock to the desired clock frequency. figure 3. power up waveforms > 20s stable clock start normal operation doff stable (< +/- 0.1v dc per 50ns ) fix high (or tie to v ddq ) k k ddq dd v v / ddq dd v v / clock start (clock starts after stable ) ddq dd v v / ~ ~ ~ ~ unstable clock [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 22 of 33 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ..... ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +2.9 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc applied to outputs in high z ........?0.5 v to v ddq + 0.3 v dc input voltage [19] ........................... ?0.5 v to v dd + 0.3 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, m 3015) ......................................... > 2001 v latch up current .................................................... > 200 ma operating range range ambient temperature (t a ) v dd [20] v ddq [20] commercial 0 c to +70 c 1.8 0.1 v 1.4 v to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 197 216 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. for more details refer to application note, accelerated neutron ser testing and calculation of terrestrial failure rates - an54908 . electrical characteristics over the operating range dc electrical characteristics over the operating range parameter [21] description test conditions min typ max unit v dd power supply voltage ? 1.7 1.8 1.9 v v ddq i/o supply voltage ? 1.4 1.5 v dd v v oh output high voltage note 22 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v ol output low voltage note 23 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?? 0.1 ma, nominal impedance v ddq ? 0.2 ? v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss ? 0.2 v v ih input high voltage ? v ref + 0.1 ? v ddq + 0.3 v v il input low voltage ? ?0.3 ? v ref ? 0.1 v i x input leakage current gnd ? v i ? v ddq ? 5 ? 5 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ? 5 ? 5 ? a v ref input reference voltage [24] typical value = 0.75 v 0.68 0.75 0.95 v notes 19. overshoot: v ih (ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5 v (pulse width less than t cyc /2). 20. power up: assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 21. all voltage referenced to ground. 22. outputs are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 23. outputs are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 24. v ref(min) = 0.68 v or 0.46 v ddq , whichever is larger, v ref (max) = 0.95 v or 0.54 v ddq , whichever is smaller. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 23 of 33 i dd [25] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 333 mhz ( 8) ? ? 370 ma ( 9) ? ? 370 ( 18) ? ? 370 ( 36) ? ? 440 300 mhz ( 8) ? ? 350 ma ( 9) ? ? 350 ( 18) ? ? 350 ( 36) ? ? 420 250 mhz ( 8) ? ? 320 ma ( 9) ? ? 320 ( 18) ? ? 320 ( 36) ? ? 370 200 mhz ( 8) ? ? 280 ma ( 9) ? ? 280 ( 18) ? ? 290 ( 36) ? ? 330 167 mhz ( 8) ? ? 260 ma ( 9) ? ? 260 ( 18) ? ? 270 ( 36) ? ? 300 electrical characteristics (continued) over the operating range dc electrical characteristics (continued) over the operating range parameter [21] description test conditions min typ max unit note 25. the operation curre nt is calculated with 50% re ad cycle and 50% write cycle. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 24 of 33 i sb1 automatic power down current max v dd , both ports deselected, v in ? v ih or v in ? v il f = f max = 1/t cyc , inputs static 333 mhz ( 8) ? ? 270 ma ( 9) ? ? 270 ( 18) ? ? 270 ( 36) ? ? 270 300 mhz ( 8) ? ? 260 ma ( 9) ? ? 260 ( 18) ? ? 260 ( 36) ? ? 260 250 mhz ( 8) ? ? 250 ma ( 9) ? ? 250 ( 18) ? ? 250 ( 36) ? ? 250 200 mhz ( 8) ? ? 250 ma ( 9) ? ? 250 ( 18) ? ? 250 ( 36) ? ? 250 167 mhz ( 8) ? ? 250 ma ( 9) ? ? 250 ( 18) ? ? 250 ( 36) ? ? 250 electrical characteristics (continued) over the operating range dc electrical characteristics (continued) over the operating range parameter [21] description test conditions min typ max unit ac electrical characteristics over the operating range parameter [26] description test conditions min typ max unit v ih input high voltage ? v ref + 0.2 ? ? v v il input low voltage ? ? ? v ref ? 0.2 v note 26. overshoot: v ih (ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5 v (pulse width less than t cyc /2). [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 25 of 33 capacitance parameter [27] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 1.8 v, v ddq = 1.5 v 4 pf c o output capacitance 4pf thermal resistance parameter [27] description test conditions 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 13.7 c/w ? jc thermal resistance (junction to case) 3.73 c/w ac test loads and waveforms figure 4. ac test loads and waveforms 1.25 v 0.25 v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75 v v ref = 0.75 v [28] 0.75 v under te s t 0.75 v device under te s t output 0.75 v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? notes 27. tested initially and after any design or process change that may affect these parameters. 28. unless otherwise noted, test conditions assume signal transition time of 2 v/ns, timing reference levels of 0.75 v, v ref = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 4 . [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 26 of 33 switching characteristics over the operating range parameter [29, 30] description 333 mhz 300 mhz 250 mhz 200 mhz 167 mhz unit cypress parameter consortium parameter min max min max min max min max min max t power v dd(typical) to the first access [31] 1?1?1?1?1?ms t cyc t khkh k clock and c clock cycle time 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns t kh t khkl input clock (k/k and c/c ) high 1.20 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns t kl t klkh input clock (k/k and c/c ) low 1.20 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.35 ? 1.49 ? 1.8 ? 2.2 ? 2.7 ? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 1.30 0.0 1.45 0.0 1.8 0.0 2.2 0.0 2.7 ns setup times t sa t avkh address setup to k clock rise 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns t sc t ivkh control setup to k clock rise (ld , r/w ) 0.4?0.4?0.5?0.6?0.7? ns t scddr t ivkh double data rate control setup to clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.3?0.3?0.35?0.4?0.5? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise0.3?0.3?0.35?0.4?0.5? ns hold times t ha t khax address hold after k clock rise 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns t hc t khix control hold after k clock rise (ld , r/w ) 0.4?0.4?0.5?0.6?0.7? ns t hcddr t khix double data rate control hold after clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.3?0.3?0.35?0.4?0.5? ns t hd t khdx d [x:0] hold after clock (k/k ) rise0.3?0.3?0.35?0.4?0.5? ns notes 29. unless otherwise noted, test conditions assume signal transitio n time of 2 v/ns, timing reference levels of 0.75 v, v ref = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 4 on page 25 . 30. when a part with a maximum frequency above 167 mhz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range. 31. this part has an internal voltage regulator; t power is the time that the power is supplied above v dd minimum initially before a read or write operation can be initiated. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 27 of 33 output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ?0.45?0.45?0.45?0.45?0.50ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns t ccqo t chcqv c/c clock rise to echo clock valid ?0.45?0.45?0.45?0.45?0.50ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns t cqd t cqhqv echo clock high to data valid ?0.25?0.27?0.30?0.35?0.40ns t cqdoh t cqhqx echo clock high to data invalid ?0.25 ? ?0.27 ? ?0.30 ? ?0.35 ? ?0.40 ? ns t cqh t cqhcql output clock (cq/cq ) high [32] 1.25?1.40?1.75?2.25?2.75? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise (rising edge to rising edge) [32] 1.25?1.40?1.75?2.25?2.75? ns t chz t chqz clock (c/c ) rise to high z (active to high z) [33, 34] ?0.45?0.45?0.45?0.45?0.50ns t clz t chqx1 clock (c/c ) rise to low z [33, 34] ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns pll timing t kc var t kc var clock phase jitter ?0.20?0.20?0.20?0.20?0.20ns t kc lock t kc lock pll lock time (k, c) [35] 20?20?20?20?20? ? s t kc reset t kc reset k static to pll reset 30?30?30?30?30? ns switching characteristics (continued) over the operating range parameter [29, 30] description 333 mhz 300 mhz 250 mhz 200 mhz 167 mhz unit cypress parameter consortium parameter min max min max min max min max min max notes 32. these parameters are extrapolated from the input timing parameters (t cyc /2 ? 250 ps, where 250 ps is the internal jitte r). these parameters are only guaranteed by design and are not tested in production. 33. t chz , t clz are specified with a load capacitance of 5 pf as in (b) of figure 4 on page 25 . transition is measured ? 100 mv from steady-state voltage. 34. at any voltage and temperature t chz is less than t clz and t chz less than t co . 35. for frequencies 300 mhz or below, the cypress qdr ii devices surpass the qdr consortium specification for pll lock time (t kc lock) of 20 s (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stabl e clock is presented, per the previous 90 nm version. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 28 of 33 switching waveforms figure 5. read/write/deselect sequence [36, 37, 38] k 1 2 3 4 5 6 7 8 9 10 11 12 13 a dq c read (burst of 4) read (burst of 4) read (burst of 4) nop nop write (burst of 4) write (burst of 4) nop dont care undefined cq k ld r/w c cq t kh t kl t cyc t khkh t sc t hc t sa t ha a0 a1 a2 a3 a4 q00 q01 q02 q03 q10 q11 q12 q13 d20 d21 d22 d23 d30 d31 d32 d33 t hd t sd t hd t sd t khch t khch t clz t doh t co t cqd t cqdoh t chz t ccqo t kh t kl t cyc t khkh t cqoh t ccqo t cqoh t cqhcqh t cqh q40 notes 36. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, that is, a0 + 1. 37. outputs are disabled (high z) one clock cycle after a nop. 38. in this example, if address a4 = a3, then data q40 = d30, q41 = d31, q42 = d32, and q43 = d43. write data is forwarded immed iately as read results. this note applies to the whole diagram. [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 29 of 33 ordering information the following table contains only the parts that are currently av ailable. if you do not see what you are looking for, contact y our local sales representative. for more inform ation, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices. speed (mhz) ordering code package diagram package type operating range 333 CY7C1321KV18-333BZC 51-85180 165-ball fine-pitch ball grid array (13 15 1.4 mm) commercial 250 cy7c1319kv18-250bzc 51-85180 165-ball fine-pitch ball grid array (13 15 1.4 mm) commercial cy7c1321kv18-250bzc cy7c1321kv18-250bzxc 165-ball fine-pitch ball grid array (13 15 1.4 mm) pb-free ordering code definitions temperature range: c = commercial = 0 ? c to +70 ?c x = pb-free; x absent = leaded package type: bz = 165-ball fbga speed grade: xxx = 333 mhz / 250 mhz v18 = 1.8 v v dd process technology: k = 65 nm part identifier: 13xx = 1319 or 1321 technology code: c = cmos marketing code: 7 = srams company id: cy = cypress cy 13xx k - xxx bz x v18 c c 7 [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 30 of 33 package diagram figure 6. 165-ball fbga (13 15 1.4 mm ) bb165d/bw165d (0.5 ball diameter), 51-85180 51-85180 *c [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 31 of 33 acronyms document conventions units of measure acronym description ddr double data rate eia electronic industries alliance fbga fine-pitch ball grid array hstl high-speed transceiver logic i/o input/output jedec joint electron devices engineering council jtag joint test action group lmbu logical multiple bit upset lsb least significant bit lsbu logical single bit upset msb most significant bit pll phase locked loop sel single event latch up sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select symbol unit of measure c degree celsius mhz mega hertz a micro amperes s micro seconds ma milli amperes mm milli meter ms milli seconds mv milli volts ns nano seconds ? ohms % percent pf pico farad vvolts wwatts [+] feedback
cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 document number: 001-58906 rev. *d page 32 of 33 document history page document title: cy7c1317k v18/cy7c1917kv18/cy7c1319kv18/cy7c1321kv18, 18-mbit ddr ii sram four-word burst architecture document number: 001-58906 rev. ecn no. orig. of change submission date description of change ** 2860800 vkn 01/20/2010 new data sheet *a 2897150 njy 03/22/2010 removed inactive parts *b 3081152 njy 11/09/2010 changed stat us from preliminary to final. updated ordering information. added ordering code definitions. added acronyms and document conventions. *c 3169007 njy 02/10/2011 added note 33. updated ordering information . *d 3321978 njy 07/20/2011 updated ordering information . updated in new template. [+] feedback
document number: 001-58906 rev. *d revised july 20, 2011 page 33 of 33 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1317kv18, cy7c1917kv18 cy7c1319kv18, cy7c1321kv18 ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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